JUMP e-Workshop: Ge NC-GAAFETs: SCE Reduction, Switch Speed, Synaptic Applications / Peide Ye (Purdue)


Location: webex

This e-Workshop is only available to the JUMP research community, such as Principal Investigators, postdoc researchers, students, and corporate sponsors. ASCENT is one of six JUMP centers administered by SRC. For access to full program information, please go to src.org. Thank you for interest in ASCENT.


The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. We apply Ge gate-all-around (GAA) nanowire MOSFETs as the test vehicles integrated with ferroelectric Hf0.5Zr0.5O2 (HZO) gate dielectric and demonstrate bi-dimensional sub-60 mV/dec operations. [1] Negative capacitance (NC) effect can further reduce the short-channel effect and improve the off-state performance of these Ge GAAFETs. [2] By ultra-fast pulse measurements, it is found that HZO could switch its polarization directly by a single pulse with the minimum pulse width of 3.6 ns. The polarization switching triggered by pulse train with pulse width as short as 100 ps is also demonstrated for the first time. [3] Finally, we also demonstrate to use Ge ferroelectric nanowire FET as synaptic device for online learning in neural network with high number of conductance state and Gmax/Gmin. [4] The work is in close collaborations with Wonil Chung, Mengwei Si, Pragya R. Shrestha, Jason P. Campbell, and Kin P. Cheung.

[1] W. Chung et al., IEDM., p. 365, 2017.
[2] W. Chung et al., DRC, 2018.
[3] W. Chung et al., VLSI, p. 89, 2018.
[4] W. Chung et al., IEDM, 2018.