Title: Cryogenic Operation of Deeply Scaled CMOS for High Performance Computing
Presenter: Wriddhi Chakraborty (Suman Datta's Group, Notre Dame)
Abstract: As we are approaching a limit in the improvement of semiconductor device performance, the primary motivation for utilizing low temperature CMOS (Cool-CMOS) technology becomes boosting the device performance with substantial reduction in power dissipation at the same time. In order to investigate and predict the response of nanoscale MOSFETs at low temperature, we extend the compact Virtual Source (VS) model for nanoscale MOSFETs from room temperature to 6K. The model is calibrated to experimental data from 30 nm channel length bulk-Si CMOS FETs. We conclude that while ballistic efficiency of nanoscale MOSFETs degrades in linear region as we approach cryogenic temperature, its ballistic efficiency improves in the saturation region at low temperature. The model is also used to project performance of Cool CMOS technology by investigating the effect of channel length and supply voltage scaling to enable low voltage cryogenic circuit design at deeply scaled nodes.
Related to task: 2776.065: DSSP - Cryogenic CMOS Logic with Record Energy-Delay Product Performance / Suman Datta (Notre Dame) / Darrell G. Schlom (Cornell)
Please note: This meeting is only available to the JUMP research community, such as Principal Investigators, Postdoc researchers, Students, and Industry/Government liaisons