Point of Load (POL) DC/DC converters and regulators are an essential part of power delivery for high-performance computing. Current solutions limit the overall power efficiency because: (i) multiple stages (3-4) of DC/DC conversion are used; (ii) multiple stages of conversion lead to larger currents flowing through board traces which induce copper losses and further reduce efficiency; (iii) discrete solutions are used that increases board real estate; (iv) the converters have reduced efficiency when load current changes are large, as is typical in digital load circuits, (v) multi-stage converters are not co-optimized across stages and often support multiple load processors simultaneously that affects both performance and energy-efficiency of the system and (vi) package parasitics and losses are large. The last stages of DC/DC power conversion have dramatic impact on the overall energy conversion efficiency in electronic systems. To address this, next generation power delivery systems are exploring 48V-1V single-stage conversion, where the converter can be placed close to the load, within the package. To reduce conductor losses, GaN based power stages are being explored along with embedded inductors to enhance system power-efficiency. This requires significant advances in (i) circuit design, (ii) active GaN device technology as well (iii) integration of high-quality inductors and (iv) advanced cooling solutions.
In this talk we will discuss all four vectors starting with a system overview and discussion of the state of the art as well as converter topologies that promise to deliver high energy-efficiency (Raychowdhury group). Next, we will discuss latest advances in P-type GaN device technology that can enable complementary GaN based power stage for high energy-efficiency (Mishra group). The final part of the presentation will include an overview of inductor technology along with package integration and cooling that is an essential part of PoL 48V/1V converter (Swaminathan group).
Arijit Raychowdhury is currently a Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology where he joined in January 2013. He is the co-director of the Georgia Tech Quantum Alliance. From 2013 to July 2019 he was an Associate Professor and held the ON Semiconductor Junior Professorship in the department. His industry experience includes five years as a Staff Scientist in the Circuits Research Lab, Intel Corporation, and a year as an Analog Circuit Researcher with Texas Instruments Inc. His research interests include low power digital and mixed-signal circuit design, design of power converters, sensors and exploring interactions of circuits with device technologies. He and his students have won eleven best paper awards and multiple fellowships and awards over the years.
Umesh K. Mishra is a Professor in the Electrical & Computer Engineering Department at the University of California, Santa Barbara (1990–Present). He is the CTO, co-founder and Chairman of Transphorm, founded in 2007 and the first company to deliver gallium nitride (GaN) transistor products for high efficiency power conversion technologies. Prior to Transphorm, he co-founded Nitres Inc. in 1996, which was the first company to develop GaN LEDs and transistors. Mishra earned a B.Tech degree from the Indian Institute of Technology Kanpur, India in 1979. He went on earn his M.S. in Electrical Engineering at Lehigh University in 1981 and Ph.D. at Cornell University in 1984 and served as a principal staff engineer at General Electric. Mishra was elected to the National Academy of Engineering in 2009 for his contributions to the development of gallium nitride electronics and other high-speed, high-power semiconductor electronic devices.
Madhavan Swaminathan is the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE) with joint appointment in the School of Materials Science and Engineering, and Director of the 3D Systems Packaging Research Center (PRC), Georgia Tech (GT). He also serves as the Site Director for the NSF Center for Advanced Electronics through Machine Learning (CAEML). He formerly held the position of Founding Director, Center for Co-Design of Chip, Package, System (C3PS), Joseph M. Pettit Professor in Electronics in ECE and Deputy Director of the Packaging Research Center (NSF ERC), GT. Prior to joining GT, he was with IBM working on packaging for supercomputers. He is the author of 500+ refereed technical publications, holds 30 patents, primary author and co-editor of 3 books, founder and co-founder of two start-up companies, and founder of the IEEE Conference Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the EPS society. His research has been recognized with 22 best paper and best student paper awards. In addition, his most recent awards include the D. Scott Wills ECE Distinguished Mentor Award (2018), the Georgia Tech Outstanding Achievement in Research Program Development Award (2017), the Distinguished Alumnus Award from the National Institute of Technology Tiruchirappalli (NITT) in India (2014), and the Outstanding Sustained Technical Contribution Award from the IEEE Components, Packaging, and Manufacturing Technology Society (2014). He is an IEEE Fellow and has served as the Distinguished Lecturer for the IEEE EMC society. He received his MS/PhD degrees in Electrical Engineering from Syracuse University in 1989 and 1991, respectively.
Please note: This e-Workshop is only available to the JUMP research community, such as Principal Investigators, postdoc researchers, students, and corporate sponsors. ASCENT is one of six JUMP centers administered by SRC. For access to full program information, please go to src.org. Thank you for interest in ASCENT.