NeuroSim Updates and Inference Engine Design with Area Constraints
Presenters: Xiaochen Peng and Anni Lu (Prof. Shimeng Yu's group, Georgia Tech)
Abstract: We will update our recent progress on the benchmark efforts on the deep learning accelerator design with compute-in-memory technologies. We recently released the latest DNN+NeuroSim V1.1 benchmark framework for inference engine design with SRAM/RRAM/PCM/FeFET, etc. We will also discuss the design strategies under the chip area constraints. For example, if the on-chip memory is not large enough to hold all the weights of the large-scale neural network model, we have to reload the weights from off-chip DRAM with appropriate scheduling.
This meeting is only available to the JUMP research community, such as Principal Investigators, Postdoc researchers, Students, and Industry/Government liaisons.