ASCENT Theme 1 Liaison Meeting / Two-Dimensional Monolayer Dichalcogenide Transistors for 3D Integration


Location: webex

Two-Dimensional Monolayer Dichalcogenide Transistors for 3D Integration

Presenters: Connor McClellan and Eric Pop (Stanford)

Abstract: We will discuss our recent progress with atomically thin two-dimensional (2D) transistors for 3D integration applications. We have grown monolayer, three-atom-thick [Mo,W][S,Se]2 semiconductors on varied substrates including SiO2, Al2O3, AlN, and on 3D sidewalls and trenches with high aspect ratio. We have recently lowered the growth temperature to 550 C, without apparent degradation in mobility vs. earlier high-temperature growths. Improving electrical contacts has led to the realization of 10-40 nm MoS2 transistors with the highest current reported to date for a monolayer semiconductor (>0.5 mA/um), near ballistic limits. Measurements of ultrawide transistors have revealed that the off-state current is as low 10 aA/um, which is normally below detectable limits in conventional test structures. We have also uncovered that ZrSe2 and HfSe2 have native high-κ dielectrics ZrO2 and HfO2, which are of key technological relevance. Ongoing work is focused on further improving device contacts, reducing defects, and further lowering the growth temperature with industry-friendly MOCVD. Throughout, we will also discuss benchmarking of 2D transistors with fundamental limits and with other technologies (see recently launched

This meeting is only available to the JUMP research community, such as Principal Investigators, Postdoc researchers, Students, and Industry/Government liaisons.