Presenters: Ankit Kaul, Carl Li, and Youngtak Lee (Prof. Muhannad Bakir's group, Georgia Tech)
Abstract: There exists a performance gap between TSV-based 3D and monolithic 3D ICs in terms of energy, bandwidth, and interconnect density. To bridge this gap, a 3D polylithic integration scheme has been proposed which represents a densely integrated system divided into multiple device tiers. Custom chiplets such as I/O PHYs, mm-wave front-ends, are embedded into the back-end of an application processor tier with a monolithic memory tier, such as an RRAM based deep neural network (DNN) inference engine. This scheme, termed 3D seamless off-chip connectivity (3D SoC+), aims to combine the best of both monolithic and TSV-based 3D ICs, including extreme efficient signaling and large bandwidth density. As an enabling technology for 3D SoC+, we first demonstrate the feasibility of using selective thermal cobalt metal (Co) ALD as high-density Cu-Cu interconnect bonding at low temperature (200 oC). Second, we present the thermo-mechanical sensitivity analysis of copper interconnects with pitch scaling down to near-1 μm and propose mitigation approaches for scaled pitch to help reduce stress below the yield strength of copper. Finally, we present the impact of 3D integration and cooling on RRAM reliability quantified by image recognition accuracy loss over time for a DNN hardware model. Worst-case accuracy drop at 10 years was estimated as 82% for air-cooling compared to 2% for liquid-cooling.
Task update on: 2776.049: Embedded Cooling, Thermal-Electrical Co-Design, and Benchmarking of Options
This meeting is only available to the JUMP research community, such as Principal Investigators, Postdoc researchers, Students, and Industry/Government liaisons.