An in-memory computing fabric for AES acceleration
Presenter: Dayane Reis, PhD candidate with Prof X. Sharon Hu and Prof. Mike Niemier (Notre Dame)
Compact, fast and low-power AES encryption/decryption engines are desirable for many edge computing applications. In this talk, we introduce our in-memory computing (IMC) fabric for AES acceleration (IMAESA), which is based on dual-mode CAM/RAM arrays. IMAESA allows for the implementation of AES with combined (Inv)SubBytes and (Inv)MixColumns steps, so as to perform encryption and decryption with a unified hardware structure. Thanks to the high parallelism of our IMC fabric, as well as our step-combination approach, IMAESA achieves high throughput AES-128 encryption/decryption. We present technology case studies for IMAESA implementation that demonstrate the impact of CMOS and FeFET on figures-of-merit including delay, area and power consumption. Finally, we compare our design to previous ASIC-based AES accelerators.
Presenter: Dayane Reis (Notre Dame)
This meeting is only available to the JUMP research community, such as Principal Investigators, Postdoc researchers, Students, and Industry/Government liaisons.