JUMP e-Workshop / Application-level benefits of emerging, embedded, non-volatile memories


Location: webex

Application-level benefits of emerging, embedded, non-volatile memories

Abstract:  We consider the evaluations of non-volatile memories (NVMs) in system deployment via collaborations between ASCENT and ADA. Within ASCENT, multiple NVM candidates are being developed, simulated, prototyped, and evaluated. Resistive random-access memory (RRAM), magento-random access memory (MRAM) (with different write mechanisms / material compositions), ferroelectric memories (e.g., ferroelectric field-effect transistors (FeFETs)), and backend of line (BEOL) compatible devices are all current targets. “On paper,” and at the cell level, all aforementioned technologies – RRAM, MRAM, FeFETs, BEOL SRAM, BEOL eDRAM – have promise. As examples, MRAM arrays have high write endurance, ideal for cache-like memories; RRAM cells are well-suited for dense, crossbar architectures; and FeFET cells enable dense, compact, and functionally rich content addressable memories (CAMs), which could be used in support of new machine learning (ML) models among others. Still, while different memory technologies have unique advantages, they also may suffer from unique drawbacks – which can impact array-level figures of merit (FOM) in different ways. MRAM’s high endurance may be offset by lower cell densities; RRAM’s density is countered by higher write times; and while FeFETs enable dense CAMs, they may also require high write voltages, which in turn leads to degradations in write energy.  SRAM also remains an attractive memory option owing to its low latency. Ultimately, the best memory for a given application will reduce the computational bottlenecks associated with that application. Furthermore, depending on the read/write characteristics of a given application, a specific “drawback” of a memory technology may be quite tolerable. The question of the true utility of a memory technology cannot be answered by ASCENT alone, and application-level case studies are required. 
More specifically, in this e-workshop, Mehdi Sharifi (Notre Dame) will begin by discussing design space explorations of ferroelectric field-effect transistors (FeFETs) – i.e., where we investigate how scaling, different write schemes, etc. all impact array-level performance metrics. Results from these efforts are incorporated into broader, comparative studies across technology proposals to evaluate the efficacy under realistic application and system constraints, as defined using ADA-driven benchmarking efforts. (Lillian Pentecost from Harvard/ADA will present this work.)  The workshop concludes with a brief discussion by Arman Kazemi (Notre Dame) as to how efforts are extensible to other cross-center collaborations (e.g., with CRISP regarding content addressable memories.)


Mohammad Mehdi Sharifi graduated from Shahid Beheshti University, Tehran, Iran in 2017 with a bachelor's in computer engineering. He started his Ph.D. at Notre Dame in 2018 and is co-advised by Dr. X. Sharon Hu and Dr. Michael Niemier. His research interests include low-power circuit design, applications for beyond-CMOS technologies, and in-memory computing. Currently, his research focuses on designing and benchmarking circuits and architecture which exploits the properties of different beyond-CMOS technologies.

Lillian Pentecost is a PhD Candidate at Harvard University seeking to explore, model, and evaluate the viability of various embedded non-volatile memory proposals for data-intensive applications, as well as working to enable design space exploration for heterogeneous future on-chip memory more generally.  She is particularly interested in cross-stack design methodologies, infrastructure, and simulation tools to co-design application-level and architecture-level constraints and optimizations with low-level memory cell characteristics for maximum potential efficiency.  She is advised by Professors David Brooks and Gu-Yeon Wei.  Previously, she completed a Masters in Computer Science at Harvard University and a BA in Physics and Computer Science from Colgate University, in addition to research internships at IBM, Microsoft Research, and NVIDIA.

Arman Kazemi is a Ph. D. student at the University of Notre Dame in the codesign lab. His research interests include hardware/software co-design, low-power hardware design, and in-memory computing. He is particularly interested in inventions leveraging emerging beyond-CMOS technologies e.g. ferroelectric materials. His research usually targets reducing computational resource requirements of machine learning applications using emerging circuits and architectures.

This meeting is only available to the JUMP research community, such as Principal Investigators, Postdoc researchers, Students, and Industry/Government liaisons.