Device and application-level analysis of multi-level FeFET memory cells
Data-intensive applications such as deep neural networks (DNNs) and graph analytics have emerged as dominating workloads in the current computing landscape and have influenced many research efforts and advances in computer architecture in the past few years. Specialized hardware architectures deliver outstanding performance and computational efficiency. However, the size and complexity of critical workloads continues to outstrip available on-chip memory capacity, making data movement and efficient on-chip storage an outstanding challenge in scaling these applications. Embedded non-volatile memories (eNVM) offer a promising alternative to traditional on-chip SRAM. Multi-level ferroelectric field effect transistors (FeFET) based embedded non-volatile memories are a promising solution for denser and more energy-efficient on-chip memory. However, reliable multi-level cell storage requires careful optimizations to minimize the design overhead costs.
More specifically, this presentation considers underlying cell-level / array-level modeling efforts (quality versus experimental results from ASCENT) and how said efforts feed into application-level benchmarking frameworks from the ADA center. More specifically, Mehdi Sharifi (ND/ASCENT, Ph.D. Student) will discuss collaborations with Kai Ni (formerly of ASCENT, now at RIT). related to single and multi-level cell FeFET design space explorations that aim to identify optimal write schemes, memory cell size scaling, etc. Extensibility to content addressable memory designs, ADA center application-level evaluation tools, feedback loop to device efforts will also be discussed in the context of silicon FeFETs. Sourav Datta (ND/ASCENT, Research Asst.Professor) will discuss BEOL transistor models and BEOL FeFET model development (with Sharifi) that will be used to extend design space exploration efforts that will eventually be ported to ADA benchmarking tools.
Theme 4, Task: 2776.083 Application-level Benefits of Emerging, Embedded, Non-volatile Memories
Mohammad Mehdi Sharifi graduated from Shahid Beheshti University, Tehran, Iran in 2017 with a bachelor's in computer engineering. He then started his Ph.D. at Notre Dame in 2018, co-advised by Dr. X. Sharon Hu and Dr. Michael Niemier. His research interests include low-power circuit design, applications for beyond-CMOS technologies, and in-memory computing. Currently, his research focuses on designing and benchmarking circuits and architecture which exploit the properties of different beyond-CMOS technologies (e.g., TIGFETs and FeFETs).
Sourav Dutta is currently a Research Assistant Professor in the Electrical Engineering department at University of Notre Dame. He received his Bachelors in Electrical Engineering from Jadavpur University, Kolkata, India, in 2012 and Ph.D. in Electrical and Computer Engineering from Georgia Institute of Technology, Atlanta, USA, in 2017 under Dr. Azad Naeemi. He was a postdoctoral research scholar in Dr. Suman Datta’s group at University of Notre Dame from 2018 - 2020. His current research focuses on emerging device architecture exploration and implementation to enable brain-inspired computing. His work involves experimental characterization, modeling and simulation of ferroelectric and phase-change materials for enabling neural networks and coupled oscillator based neuromorphic hardware. Previously, he has worked on modeling and simulation of spintronic devices and interconnects for Beyond-CMOS application during his PhD. From May to July 2016, he was a visiting researcher at IMEC, Belgium where he was involved in modeling and simulation of nanoscale plasmonic logic gates, magneto-plasmonics and spin-plasmonics for boolean and non-boolean computation for Beyond-CMOS application. Sourav is the recipient of the 2018 Sigma Xi Best Ph.D. Thesis Award at Georgia Tech and 2009 Kishore Vaigyanik Protsahan Yojana (Young Scientist Encouragement Program) Fellowship in India.
This meeting is only available to the JUMP research community, such as Principal Investigators, Postdoc researchers, Students, and Industry/Government liaisons.