Rapid Design Space Exploration of Neuromorphic Hardware using Emerging Devices
Date: Sept 16
Time: 4:00pm eastern
Theme 4, Task: 2776.074: Neuromorphic Design Flow / PI Siddharth Joshi (NotreDame)
Abstract: Neuromorphic accelerators for the edge are constrained by energy, area, and delay, and consequently occupy various points in the design space defined by different mappings, architectures, and devices. The interactions between these choices remain underexplored. Our goal is to rapidly traverse this design space, enabling the design and evaluation of heterogenous digital and Compute in Memory (CiM) architectures that explore these tradeoffs in neuromorphic applications. In this talk, we will present a novel way of designing the mapspace and evaluate the mapspace on different workloads, architectures, and devices. We will also discuss in depth the impact of sparse characteristics using different representations for Spiking Neural Network (SNN) applications on dataflow accelerator designs. A sparse aware design can avoid unnecessary access to memory and number of computations, and storage (using compression methods) which leads to lower energy, cycles, and area. Throughout all this, we will enable rapid evaluation of different architectures that might use ASCENT devices. Early results show a range of 2x-100x improvement in energy in a modeled heterogeneous architecture.
Bios: Mark Horeni is a PhD student in the department of Computer Science and Engineering at the University of Notre Dame. His interests lie trying to solve neuromorphic engineering problems. This takes the form of examining different representations of information, to studying how properties of emerging devices can be used as solutions to problems. As an undergraduate at Lewis University, he did research into the connectome of the C. elegans roundworm to analyze the predictive power of the links between neurons.
Pooria Taheri is a PhD student in the department of Computer Science and Engineering at the University of Notre Dame. His research interest revolves around designing accelerators using emerging technologies for machine learning applications more specifically Spiking neural networks (SNN). Before joining the University of Notre Dame, he graduated from National University of Iran, and his research was mostly focused on parallel computations for classification algorithms e.g. k-means and VLSI designs. He also worked as a junior researcher at IPM (Institute for research in Fundamental Science).
This meeting is only available to the JUMP research community, such as Principal Investigators, Postdoc researchers, Students, and Industry/Government liaisons.