ASCENT Theme 4 / N40 RRAM Compute-in-Memory Macro without ADC and with Built-in Error Correction

Date: Jan 27, 2022

Time: 4:00pm ET/3:00pm CT/ 1:00pm PT

Title: N40 RRAM Compute-in-Memory Macro without ADC and with Built-in Error Correction

Presenters: Hongwu Jiang & Wantong Li  Georgia Tech (Prof. Shimeng Yu's group)

Short Summary: In this talk, we will present two recent macro designs with TSMC N40 RRAM process. The first macro features the ADC-free analog communication between RRAM compute-in-memory (CIM) subarrays. The design relies on the edge capacitor and a ramp generator to convert partial sum current to the pulse-width-modulation (PWM) signal to realize the ADC-free communication. The related architecture-level design issues will be also addressed. The second macro features the built-in error correction code (ECC) that is compatible with the parallel compute of CIM subarrays. The goal of ECC here is not to protect the individual bit but to protect the partial sum as a whole. Both macros were taped-out with TSMC N40 RRAM process and achieved competitive energy efficiency (TOPS/W) while providing more advantages than prior designs

ASCENT Tasks: 2776.039 and 2776.045

This meeting is only available to the JUMP research community, such as Principal Investigators, Postdoc researchers, Students, and Industry/Government liaisons.