Title: Supporting cross-layer design space exploration for content addressable memories
Time: 4:00pm eastern time
- Students: Liu Liu, University of Notre Dame; Mehdi Sharifi, University of Notre Dame;
- Faculty: X. Sharon Hu, University of Notre Dame; Michael Niemier, University of Notre Dame
Content addressable memories (CAMs), a special-purpose in-memory computing (IMC) unit, support parallel searches directly in memory. There is growing interest in CAMs for data-intensive applications such as machine learning and bioinformatics. The design space for CAMs is large and rapidly expanding. In addition to traditional binary and ternary CAMs (TCAMs), analog CAM (ACAM) and multi-bit CAM (MCAM) designs based on various non-volatile memory (NVM) devices being developed in the ASCENT center/elsewhere have recently been introduced, and may offer advantages over CMOS-based solutions across various figures of merit (FOM) and/or enable new compute functionality.
A representative example of our recent work considers end-to-end evaluations of ferroelectric-based, multi-bit content addressable memories that can efficiently support hyperdimensional computing (HDC) workloads [eWorkshop e007542, 2/15/22]. That said, analogous studies to the work on HDC are time consuming, due to the need for (i) detailed device-level modeling, (ii) memory cell/circuit studies, (iii) algorithm-to-hardware mapping, and (iv) the development of a suitable, at-scale architectural framework to properly evaluate meaningful, application-level workloads.
In this meeting, we begin by discussing device-level modeling efforts and memory cell design studies from ASCENT. We then discuss how this research may be coupled with Eva-CAM – a circuit/architecture-level modeling and evaluation tool for CAMs – to support rapid design space explorations of technology driven solutions to more quickly cull a vast design space. Eva-CAM supports TCAM, ACAM, and MCAM designs implemented in non-volatile memories, for exact, best and threshold match types. It also allows for the exploration of CAM array structures and sensing circuits. Eva-CAM has been validated with HSPICE simulation results and chip measurements.
2776.075: Hardware and Programming Models Supporting In-memory Accelerators for Secure Information Processing
2776.083: Application-level Benefits of Emerging, Embedded, Non-volatile Memories
X. Sharon Hu is a Professor at the University of Notre Dame. Her research interests include low-power system design, circuit and architecture design based on emerging technologies, real-time embedded systems, and hardware-software co-design. Some of her recognitions include the Best Paper Awards from DAC and ISLPED. She has participated in several large industry and government sponsored center-level projects and was a theme lead in an NSF/SRC E2CDA project. She was the General Chair of DAC in 2018 and was the TPC chair of DAC in 2015. She is the Editor-in-Chief of ACM Transactions on Design Automation of Electronic Systems, and has also served as Associate Editor for a number of ACM and IEEE journals. X. Sharon Hu is a Fellow of ACM and IEEE.
Michael Niemier is a Professor at the University of Notre Dame. He is interested in designing, facilitating, benchmarking, and evaluating circuits and architectures based on emerging logic, memory, and storage technologies for at-scale workloads/problems. He is the recipient of multiple IBM Faculty Awards, the Rev. Edmund P. Joyce, C.S.C. Award for Excellence in Undergraduate Teaching, and best paper awards such as at ISLPED. Niemier has served on numerous TPCs for design related conferences, and has chaired the emerging technologies track at DATE, DAC, and ICCAD. He is an associate editor for IEEE Transactions on Nanotechnology, as well as the ACM Journal of Emerging Technologies in Computing.
This meeting is available to the JUMP research community, such as Principal Investigators, Postdoc researchers, Students, and Industry/Government liaisons.