JUMP e-Workshop: A Moore’s law for Packaging/ Subramanian Iyer (UCLA)


Location: Via Webex

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This e-Workshop is only available to the JUMP research community, such as Principal Investigators, postdoc researchers, students, and corporate sponsors. ASCENT is one of six JUMP centers administered by SRC. For access to full program information, please go to src.org. Thank you for interest in ASCENT.

While Silicon has scaled aggressively by over a factor of a few thousand over the last six decades the progress in packaging has been more modest – a linear factor 4-5 in most cases. In this talk, we will describe the work done at UCLA to close this gap. We take two approaches: 

(1) The Silicon Interconnect Fabric (Si IF) where we aim to replace conventional organic packages and printed circuit boards with a silicon-based interconnect fabric (Si IF). We have developed processes that allow us to integrate heterogeneous dies at a die-to-substrate pitch of <10 µm using solderless copper based thermal compression bonding (TCB). The Si IF trace pitch can be <2 µm with up to four wiring levels. We will describe our approaches for power delivery, external connectors and thermo-mechanical engineering of a large SoW as well as preliminary reliability studies and electrical results that show latencies, bandwidth per mm and energy per bit values that approach SoC values. 

(2) Fan-Out Wafer-Level Packaging (FOWLP) adapted to Flexible biocompatible assemblies using PolyDiMethylSiloxane (PDMS) we have been able to demonstrate dies shifts of less than 6 µm and die co-planarity of <1µm and inter-die connection pitches of <20 µm with an array of 40 die with up to two levels of flexible corrugated interconnects. We show that these assemblies are able sustain over 2000 folding cycles with no degradation of electrical properties. A seven-segment flexible display application will be described demonstrated.
Our two complementary approaches show promise for a sustainable Moore’s Law for packaging.