ASCENT Theme 3 Liaison Meeting / 3D Heterogeneous Integration using SiO2 Encapsulation and Thermal Implications of 3D Architectures on BEOL RRAM Performance

3D Heterogeneous Integration using SiO2 Encapsulation and Thermal Implications of 3D Architectures on BEOL RRAM Performance

Abstract: There exists a performance gap between TSV-based 3D and monolithic 3D ICs in terms of energy, bandwidth, and interconnect density. To bridge this gap, a 3D polylithic integration scheme has been proposed which represents a densely integrated system divided into multiple device tiers. Custom chiplets such as I/O PHYs, mm-wave front-ends, are embedded into the back-end of an application processor tier with a monolithic memory tier, such as an RRAM based deep neural network (DNN) inference engine. This scheme, termed 3D seamless off-chip connectivity (3D SoC+), aims to combine the best of both monolithic and TSV-based 3D ICs, including extreme efficient signaling and large bandwidth density. As an enabling technology for 3D SoC+, we first briefly review the previous demonstration of Co ALD bonding and current plans. The thermomechanical designs consider the impacts of Co ALD on bonded chips and interconnects from the package perspective and the mitigation effort is addressed to reduce the stress of the interconnects. Second, a new type of multi-tier Fan-out Wafer Level Package by low temperature PECVD SiO2 encapsulation has been proposed to demonstrate high density inter-tier connectivity. Next, we present the impact of 3D integration and cooling on RRAM reliability quantified by image recognition accuracy loss over time for a DNN hardware model. Finally, results from thermal evaluation of multi-tier TSV-based 3D compute-in-memory (CIM) accelerators are presented.

Presenters: Carl Li, Youngtak Lee, and Ankit Kaul from Dr. Muhannad Bakir’s group

This meeting is only available to the JUMP research community, such as Principal Investigators, Postdoc researchers, Students, and Industry/Government liaisons.