ASCENT Theme 4 Liaison Meeting / Limits on the memory window due to interfacial polarization screening in front-end FEFETs – A combined experimental-modeling study

Title: Limits on the memory window due to interfacial polarization screening in front-end FEFETs – A combined experimental-modeling study

Speakers: Nujhat Tasneem (graduate student)  and Asif Khan (Georgia Tech) 

Abstract: One of the fundamental challenges of today’s front-end FEFETs is that the Vt window (Vt) is much smaller than its theoretical limit (2EcTF), even when operating on a major hysteresis loop (i.e., even with complete switching of the ferroelectric polarization). This occurs because only a small fraction of the FE polarization (1-10%) gets reflected in the semiconductor as charge carriers. Here, we show that the screening of ferroelectric polarization at the FE-IL interface during switching by traps can quantitatively capture the aforementioned memory window degradation. We fabricated p-type FEFETs with 5 nm ZrO2 as test vehicles. Our FEFET model, by incorporating screening via a dissipative (leakage) current through the IL in a self-consistent Preisach—Boltzmann solver, can match both the MW window in ID-VG characteristics and the minor and major hysteresis loops in the FEFET measured from the gate terminal, with remarkable accuracy for the same set of model parameters.

Insights into design strategies for front-end FEFETs to achieve reasonable MWs for logic compatible write voltages (<1.5 B) will be discussed.

This meeting is only available to the JUMP research community, such as Principal Investigators, Postdoc researchers, Students, and Industry/Government liaisons.