JUMP e-Workshop / How do we quantify the application-level benefits of a new technology? A fundamental question for ASCENT


Location: webex

Michael Niemier and Sharon Hu (University of Notre Dame)Michael Niemier and Sharon Hu (University of Notre Dame)

Speakers: Michael Niemier and X. Sharon Hu, University of Notre Dame, ASCENT

Title: How do we quantify the application-level benefits of a new technology? A fundamental question for ASCENT

Abstract: Researchers in ASCENT are working to build more efficient and/or higher performance logic devices, memory devices, and/or fabrics where processing logic and data storage are integrated at finer granularities.  The latter is especially appealing owing to challenges with the omnipresent processor-memory bottleneck, which exacerbates the efficient and expeditious processing of modern workloads.
A new device may (1) serve as a replacement for an existing technology, in an existing architecture (e.g., a new memory cell in a traditional array), or (2) serve as an “enabler” of a new circuit architecture and/or compute functionality (e.g., a new memory cell that can natively perform an important compute kernel).  For (2), it is imperative to consider if (a) a new technology can perform said kernel more efficiently when compared to either CMOS and/or an existing architectural solution, (b) if said kernel can be used broadly – for a range of applications and/or within an application to justify investment, and (c) if said kernel fundamentally changes an existing algorithm – e.g., which may impact accuracy in a machine learning task.
In this eWorkshop, we consider use case (2) via CRISP-based collaborations. We study the impact of different technology-enabled, content addressable memory (CAM)-based, in-memory matching functions as applied to hyperdimensional computing problems.  (1) We highlight the efficacy of multi-bit and analog CAMs when used to implement and analyze hypervectors via native distance functions, and compare solutions to approaches with higher dimensional precision/cosine distance functions; (2) We discuss how realistic implementation constraints including (a) the inherent precision of technology-based CAM solutions, (b) CAM architectures with appropriately sized sub-arrays to accommodate realistically-sized hypervectors, and (c) inherent device variations can be overcome to match the accuracy of GPU-based realizations; (3) We quantify (a) the impact of tradeoffs associated with technology-based solutions (e.g., longer hypervectors, peripheral circuitry to aggregate results from CAM sub-arrays, etc.) that may be needed to achieve iso-accuracy with existing solutions, (b) the resulting impact of energy and latency at the application-level, and (c) what parts of an existing workload technology-based solutions can accelerate / what the next design targets should be to achieve further improvements.

We conclude with a roadmap that illustrates how technology-based CAM solutions are applicable to a broad set of “at-scale” problems (e.g., applications in the MLPerf suite, bioinformatics workloads, etc.), how we might perform targeted/smart searches in extremely large subarrays (either in-memory, or in-storage), etc.

Michael Niemier is a Professor at the University of Notre Dame.  He is interested in designing, facilitating, benchmarking, and evaluating circuits and architectures based on emerging logic, memory, and storage technologies for at-scale workloads/problems. He is the recipient of multiple IBM Faculty Awards, the Rev. Edmund P. Joyce, C.S.C. Award for Excellence in Undergraduate Teaching, and best paper awards such as at ISLPED.  Niemier has served on numerous TPCs for design related conferences, and has chaired the emerging technologies track at DATE, DAC, and ICCAD.  He is an associate editor for IEEE Transactions on Nanotechnology, as well as the ACM Journal of Emerging Technologies in Computing.
X. Sharon Hu is a Professor at the University of Notre Dame. Her research interests include low-power system design, circuit and architecture design based on emerging technologies, real-time embedded systems, and hardware-software co-design. Some of her recognitions include the Best Paper Awards from DAC and ISLPED. She has participated in several large industry and government sponsored center-level projects and was a theme lead in an NSF/SRC E2CDA project. She was the General Chair of DAC in 2018 and was the TPC chair of DAC in 2015. She is the Editor-in-Chief of ACM Transactions on Design Automation of Electronic Systems, and has also served as Associate Editor for a number of ACM and IEEE journals.  X. Sharon Hu is a Fellow of ACM and IEEE.

This meeting is only available to the JUMP research community, such as Principal Investigators, Postdoc researchers, Students, and Industry/Government liaisons.